1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to integrated circuits including static random access memory devices.
2. Description of the Related Art
Types of semiconductor memory include dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM includes memory cells having a relatively simple structure, in particular memory cells wherein an amount of charge stored in a capacity is used to represent a bit of information. Due to the simple structure of DRAM cells, a high density of integration may be obtained. However, due to leakage currents in the capacities, DRAM typically requires constant refresh cycles to avoid a loss of information.
In SRAM devices, cross-coupled inverters are used for storing information. In SRAM devices, refresh cycles need not be performed, and they typically allow a greater speed of operation than DRAM devices. However, SRAM includes memory cells which typically have a more complex structure than the memory cells of DRAM devices, which may limit the density of integration of SRAM devices that may be obtained.
SRAM devices include an array of SRAM cells, wherein each SRAM cell can store one bit of information. In addition to single port SRAM cells, types of SRAM cells that may be used in SRAM devices include dual port SRAM cells, wherein each SRAM cell has two ports. The two ports of each SRAM cell can allow simultaneous reading of the bit stored in the SRAM cell from both ports. Moreover, in some situations, a read operation of a first SRAM cell may be performed simultaneously with a write operation on a second SRAM cell.
A layout of a conventional dual port SRAM cell 100 will be described with reference to FIG. 1. The dual port SRAM cell 100 may be provided in and/or on a P-doped substrate 101, wherein an N-well region 102 and two P-well regions 103, 104 are formed. The P-well regions 103, 104 are provided on opposite sides of the N-well region 102. The N-well region 102 and the P-well regions 103, 104 may be provided in a semiconductor material, for example silicon, of the substrate 101, wherein the N-well region 102 is doped with an N-type dopant, and the P-well regions 103, 104 are doped with a P-type dopant.
In the N-well region 102, active regions 105, 106 of a first pull-up transistor 107 and a second pull-up transistor 108, respectively, are formed. In the first P-well region 103, a first pull-down transistor 109 is provided at an active region 110. In the second P-well region 104, a second pull-down transistor 111 is provided at an active region 112.
Gate electrodes of the first pull-up transistor 107 and the first pull-down transistor 109 are provided by a line 113 of an electrically conductive material, for example doped polysilicon that is electrically connected to a drain region of the second pull-up transistor 108 by a contact structure 114. Gate electrodes of the second pull-up transistor 108 and the second pull-down transistor 111 are provided by an electrically conductive line 115 that is electrically connected to a drain area of the first pull-up transistor 107 by a contact structure 116. Metallization lines 117, 118 and contact structures 114, 116, 119, 120 provide an electrical connection between the drains of the pull-up transistors 107, 108 and their associated pull-down transistors 109, 111.
Source areas of the pull-up transistors 107, 108 may be electrically connected to a high voltage power supply line (not shown) by contact structures 121, 122, and source regions of the pull-down transistors 109, 111 may be electrically connected to a low voltage power supply line (not shown) by contact structures 123, 124.
For reading data from and writing data to the dual port SRAM cell 100, access transistors 125, 126 may be provided in the first P-well region 103 and access transistors 127, 128 may be provided in the second P-well region 104. Gate electrodes of the access transistors 125, 126 are provided by an electrically conductive line 129, and gate electrodes of the access transistors 127, 128 are provided by an electrically conductive line 130.
The access transistor 125 may be formed at the same active region 110 as the first pull-down transistor 109. The access transistor 127 may be formed at the same active region 112 as the second pull-down transistor 111. The access transistor 126 may be provided at an active region 131, and the access transistor 128 may be provided at an active region 132. An isolation structure 133, for example a shallow trench isolation structure, may provide electrical insulation between the active regions 107, 108, 110, 112, 131, 132.
The access transistor 125 has one source/drain region that is contiguous with the drain region of the first pull-down transistor 109. The other source/drain region of the access transistor 125 is electrically connected to a first bitline (not shown) by a contact structure 134. One source/drain region of the access transistor 126 may be electrically connected to the drain region of the second pull-down transistor 111 by a contact structure 135, the electrically conductive line 113, the contact structure 114, the metallization line 117 and the contact structure 119. The other source/drain region of the access transistor 126 may be electrically connected to a first inverse bitline (not shown) by a contact structure 136. The electrically conductive line 129 providing the gate electrodes of the access transistors 125, 126 may be electrically connected to a first wordline (not shown) via contact structure 137.
The access transistors 125, 126 provide a first port of the dual port SRAM cell 100. For reading data from the dual port SRAM cell 100 or writing data to the dual port SRAM cell 100 through the first port, the access transistors 125, 126 may be switched into an electrically conductive state by applying an appropriate signal to the first wordline, and a bit signal and an inverse bit signal, respectively, may be read from the first bitline and the first inverse bitline, or written to the first bitline and the first inverse bitline.
One source/drain region of the access transistor 127 may be contiguous with the drain region of the second pull-down transistor 111, and the other source/drain region of the access transistor 127 may be electrically connected to a second inverse bitline (not shown) by a contact structure 138. One source/drain region of the access transistor 128 may be electrically connected to the drain region of the first pull-down transistor 109 by a contact structure 139, the electrically conductive line 115, the contact structure 116, the metallization line 118 and the contact structure 120. The other source/drain region of the access transistor 128 may be electrically connected to a second bitline (not shown) by a contact structure 140. The electrically conductive line 130 providing the gate electrodes of the access transistors 127, 128 may be electrically connected to a second wordline by a contact structure 141.
The access transistors 127, 128 provide a second port of the dual port SRAM cell 100. Data may be read from and written to the dual port SRAM cell 100 through the second port by applying an appropriate wordline signal to the second wordline, and by reading bit signals and inverse bit signals from the second bitline and the second inverse bitline, or writing bit signals and inverse bit signals to the second bitline and the second inverse bitline.
The source and drain regions of the pull-up transistors 107, 108 may be doped inversely to the doping of the N-well region 102, i.e., P-doped. Thus, the pull-up transistors 107, 108 are P-channel transistors. The source and drain regions of the pull-down transistors 109, 111 and the source/drain regions of the access transistors 125, 126, 127, 128 may be doped inversely to the doping of the P-well regions 103, 104, i.e., N-doped, so that the pull-down transistors 109, 111 and the access transistors 125, 126, 127, 128 are N-channel transistors.
As can be seen from FIG. 1, a channel width of the pull-down transistors 109, 111, the channel width being an extension of the channel region in a direction (horizontal in the view of FIG. 1) that is perpendicular to a channel length direction from the source region to the drain region may be greater than channel widths of the other transistors of the dual port SRAM cell 100. In particular, the channel width of the pull-down transistors 109, 111 may be greater than the channel width of the access transistors 125, 127 which are formed at the same active regions 110, 112 as the pull-down transistors 109, 111. Thus, parallel operation of the dual port SRAM cell 100 via the two ports of the dual port SRAM cell 100, which may entail a relatively high current through the pull-down transistors, may be supported.
Due to optical effects occurring in the formation of dual port SRAM cell 100 by means of techniques of photolithography, the greater width of the portions of the active regions 110, 112 wherein the pull-down transistors 109, 111 are provided may entail a different effective width of the portions of the active regions 110, 112 wherein the access transistors 125, 127 are formed.
Therefore, the access transistors 125, 127 may obtain a different channel width than the access transistors 126, 128, so that the electrical parameters of the pairs of access transistors providing the two ports of the dual port SRAM cell 100 do not match.
For addressing this issue, in U.S. Pat. Nos. 8,009,463 and 8,189,368, it has been proposed to provide a different layout of dual port SRAM cells. In this layout, pairs of pull-down transistors are provided instead of each of the pull-down transistors 109, 111 described above. However, in the layout proposed in U.S. Pat. No. 8,009,463 and U.S. Pat. No. 8,189,368, electrically conductive lines providing gate electrodes of the pull-up transistors and the pairs of the pull-down transistors have a relatively complex shape including U-shaped portions that provide the gate electrodes of the pairs of pull-down transistors. This complex shape of electrically conductive lines may make manufacturing of the electrically conductive lines difficult, in particular in SRAM devices wherein small feature sizes are employed.
In view of the situation described above, the present disclosure is related to a device and a method wherein some or all of the above-mentioned issues are overcome substantially completely or at least partially.